Whos on First! Whats on Second! And, IDonKnow what a VLIW is!

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A Man Crying Alone In The Wilderness - 18 Dec 2005 13:07 GMT

There are many referances to VLIW, dating back to before my
definition's usage,
( ***another*** VLIW ref URL,
http://www.cs.duke.edu/courses/cps220/fall01/lectures/MAJC-HC99sm.pdf ,
IBM has other definitions, INTEL doesn't have a clue how to build the
ultimate efficient chip )

HOWEVER, VLIW is also a 16-bit instruction streaming protocol for SMP
MPP FORTH.

VLIW is simply a cache pre-load size-of instruction block operation.

The maximum load size of a VLIW instruction block is 4095 words, 4096
if including the VLIW cache load instruction itself, otherwise, a VLIW
object size of zero, although possible to encode, is an illegal usage
error.

The VLIW protocol stream data at three levels,A) 16-bit ( single),
32-bit ( double) and 64-bit ( quad) words, B) chip RAM buffer internal
using 512-bit to 2048-bit of RAM segment cache micro-blocks, and C) the
object level of up to 4096 16-bit words of cache pre-load, (
optionally, lockable cache is gaurded thru a sixteen level harware bus
protocol layer),

VLIW for SMP MPP FORTH is an MIMD architecture, not SIMD; ( SIMD may be
emulated thru MIMD, however, SIMD is ( very) inefficient in emulating
MIMD)
( a MIMD ref URL, http://www.ics.forth.gr/carv/bufxbar/ )
( a better MIMD ref URL,
http://groups.google.com/group/comp.lang.java.machine/browse_frm/thread/c82030e6
e901c8f5/bd00007a63ce9072

)

Regards,
maw

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rickman - 18 Dec 2005 15:27 GMT

... snipped various statements ...

> VLIW for SMP MPP FORTH is an MIMD architecture, not SIMD; ( SIMD may be
> emulated thru MIMD, however, SIMD is ( very) inefficient in emulating
> MIMD)

Yes, but SIMD is much more efficiently built in hardware and uses
memory bandwidth more efficiently. The real difference is that SIMD is
harder to program in a useful way, that is, a way that does not
degenerate to SISD usage. Of course if you are working with
applications that lend themselves to SIMD programming, then SIMD can be
a very efficient way to design the hardware and code the software.
Most signal processing applications fall into this category. Sonar
beamforming is an excellent example or phased array radar is another.
Even a simple equalizer can be efficently implemented in SIMD. The
video applications are huge! Imagine a MPP built with the image chip
that has a processor on every pixel: light in and coded video out!

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A Man Crying Alone In The Wilderness - 18 Dec 2005 15:51 GMT

> ... snipped various statements ...
> > VLIW for SMP MPP FORTH is an MIMD architecture, not SIMD; ( SIMD may be
[quoted text clipped - 12 lines]
> video applications are huge! Imagine a MPP built with the image chip
> that has a processor on every pixel: light in and coded video out!

THE Toshiba/IBM Cell efforts a simple generic MPP with graphics
problem specific extension instructions.

maw

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Alex Gibson - 24 Dec 2005 06:49 GMT

>> ... snipped various statements ...
>> > VLIW for SMP MPP FORTH is an MIMD architecture, not SIMD; ( SIMD may be
[quoted text clipped - 17 lines]
>
> maw

The cradle Mdsp chips are similar.
www.cradle.com
http://en.wikipedia.org/wiki/Mdsp
multi processor dsp chips made up of multiple risc and dsp cores.
The risc cores are used for controlling the dsp cores(floating point).
CT3400 6 general purpose cores and eight dsp cores
CT3600 8 - 16 dsp cores and 4 - 8 general purpose cores.

Programmed in a mix of c and clasm (c like assembler)
via gcc port(not free).

Cradle claim them to be the worlds most powerful dsp chip.

Alex

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A Man Crying Alone In The Wilderness - 24 Dec 2005 15:48 GMT

> >> ... snipped various statements ...
> >> > VLIW for SMP MPP FORTH is an MIMD architecture, not SIMD; ( SIMD may be
[quoted text clipped - 22 lines]
> http://en.wikipedia.org/wiki/Mdsp
> multi processor dsp chips made up of multiple risc and dsp cores.

Using Mr. Moore's 25X model ( syncronized or his asychronous model) of
hundredes of misc cores connecting to form a fabrique' for an
any-to-any channel crossbar multiplexed with my two bus ( dual bus VLIW
SMP MPP FORTH hardware protocol ) and SIMPLY modify his 25X's diagonal,
people can derive dozens of VERY high efficiency circuits, for
applications from DSP thru ATM!.

I'm not sure by what metric /powerful/ is unless you are Intel
monopolism.

I now say "logic circuit efficiency is a metric of the maximum,
non-redundant, usage of the minimum count of channels and transistors
that form a logic circuit."

maw

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Alex Gibson - 27 Dec 2005 11:30 GMT

>> The cradle Mdsp chips are similar.
>> www.cradle.com
[quoted text clipped - 7 lines]
> people can derive dozens of VERY high efficiency circuits, for
> applications from DSP thru ATM!.

2400Mips doesn't beat the higher end TI C6400's or the cradle chips.

> I'm not sure by what metric /powerful/ is unless you are Intel
> monopolism.

With dsp's usually the amount of multiply and accumulates you can do every
second
along with input/output and memory bandwidth.

With video the frame rate ( 0 - 30fps) and resolution for encode / decode
and additional image processing.
Current basic target for a lot of applications is D1 or SDTV(standard
definition digital).
720 by 576 (then can handle both pal and ntsc)
More and more apps need / will need HDTV resolution 1080i or 1080p
1920 by 1080.

Intel monopolism ??

PC chips ain't suitable for what we do.
Suck to much power, need supporting chipsets so take up to much pcb space
and can't do general purpose io - i.e easily interface to sensors and common
buses - i2c , can , spi

> I now say "logic circuit efficiency is a metric of the maximum,
> non-redundant, usage of the minimum count of channels and transistors
> that form a logic circuit."
>
> maw

Does high efficiency really matter ? as long as the power use is reasonably
low/acceptable
and you get the required amount of processing power
in an easy to program and easy to interface package at a decent cost.

That is doesn't exceed the power or thermal budgets especially if the box
its in
is exposed to all weather conditions from -30 to +55 degrees centigrade
and is powered via power over ethernet using cat 5 cable for power and data.

Alex

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A Man Crying Alone In The Wilderness - 28 Dec 2005 12:08 GMT

> <big snip>
>
[quoted text clipped - 11 lines]
>
> 2400Mips doesn't beat the higher end TI C6400's or the cradle chips.

Mr. Moore's chip claims 60,000 RAW MIPS in comparison.

Intel has known about VLIW SMP MPP FORTH computer chip formula for
almost ten years.
Intel has sold hundreds of billions in American dollars of ( obsolete)
technology.
( RE: Why hasn't Intel informed the public of technology news? )

Please quote from what I ( or Mr. Moore or anyone) have already
written,
maybe start here for the VLIW SMP MPP FORTH computer chip design
formula,
URL,
http://groups.google.com/group/comp.lang.java.machine/msg/bd00007a63ce9072?dmode
=source&hl=en

---

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A Man Crying Alone In The Wilderness - 21 Dec 2005 23:06 GMT

To alleviate some confusion for less experienced readers, my usage is
Variable Length Instruction Word ( VLIW) and is for the vast majority
of application and system software uses, SIMD's usage of VLIW is Very
Long Instruction Word ( VLIW) and are of limited applications, as
stated previously. Further, for those ( few) applications that do work
well with SIMD, /glue/ circuits/chips are almost always required.

VLIW SMP MPP enhanced stack machine architecture is still the most
efficient architecture around with me. ( the greatest utilization of
the least number of transistors and I have estimated, given equal
fabrication technology, about ten to one hundred times the performance
of a 80x86( Intle) based architecture by type of application, on the
normal. VLIW SMP MPP FORTH, like other architectures, can accommodates
specialized chips, also.)

Imaging a MPP ... you may need one of these ...
URL,
http://groups.google.com/group/comp.lang.java.machine/msg/b400d03ddc0f5a4f?dmode
=source&hl=en

washburn

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